(1) Field of the Invention
The present invention relates to a program re-writing apparatus which performs dependence relaxation for a command series including a memory access command in particular.
(2) Description of the Related Art
In recent years the processing speed of processors has substantially increased, however in comparison improvements in access speed for the main memory of a computer have been meager, and the speed difference between processors and the main memory continues to increase. Thus, it has been pointed out that conventionally, when high-speed information processing is performed by an information processing apparatus with a processor, memory access can become bottlenecked.
In order to solve this problem, one well-known method executes a load command necessary for a penalty cycle used for acquiring data stored in the memory region of the main memory, with as much priority over other commands as possible, and schedules commands such that other commands are executed during the penalty cycle. Thus, the effect of the penalty can be hidden in the execution cycle of other commands due to the memory access, and drops in performance can be prevented.
However in most cases, the memory access address value of a memory access command changes dynamically in static command scheduling. Thus memory dependence occurring during the memory access command period must be anticipated. This is known as ambiguous memory dependence. As a result, it is not possible to prioritize a load command over other memory access commands in static command scheduling, it becomes difficult to hide the penalty cycle due to the memory access command and the power of the processor cannot be taken advantage of.
Therefore, conventionally, when the processor does not have hardware which executes a special command, a load command cannot be shifted in front of the Store command for the memory region to perform command scheduling for the memory access command with an ambiguous memory dependence.
Speculative load commands are an example of a special command for addressing ambiguous memory dependence (see for example, Patent Document: U.S. Pat. No. 3,762,597 Publication (FIG. 6). A speculative load command is a command which executes the processes such as those below. In other words, the address of a memory region to be accessed by the load command is stored in a storage apparatus with special hardware and the memory data stored in the address is set in the register. Subsequently, when a store command is executed, the data stored in the register is set in the memory region. Further, when interference occurs between the address of the memory region accessed by the store command and the address of the speculative load command stored in the special storage apparatus above, data stored in the register by the store command is overwritten in the register which is set by the speculative load command. Thus, logical equivalency is maintained.
A speculative load command is explained in detail using FIG. 1, FIG. 2A and FIG. 2B.
For example, consider a processor which executes only a normal memory access command. FIG. 1 is a diagram which shows an example of a source program. FIG. 2A is a diagram which shows an example of an assembler file which is equivalent to the source program shown in FIG. 1 and does not include a speculative load command. In order to execute the memory access process shown in FIG. 1 with this kind of processor, an assembler file must be created which faithfully follows the memory access order shown in FIG. 2A.
On the other hand, FIG. 2B is a diagram which shows an example of an assembler file which is equivalent to the source program shown in FIG. 1 and includes a speculative load command. In this way, by utilizing the speculative load command, there is no longer a need to follow the memory access order shown in FIG. 1. In other words, the load command can be executed with priority over the store command. Thus the penalty cycle caused by memory referencing can be hidden in other commands and as a result the functionality of the program re-writing apparatus improves.
However, in order to execute this kind of speculative execution command, special hardware must be installed in the processor.